The semiconductor processing industry continues to strive for larger production yields while increasing the uniformity of layers deposited on substrates having larger surface areas. These same factors in combination with new materials also provide higher integration of circuits per unit area of the substrate. As circuit integration increases, the need for greater uniformity and process control regarding layer thickness rises. As a result, various technologies have been developed to deposit layers on substrates in a cost-effective manner, while maintaining control over the characteristics of the layer.
Chemical vapor deposition (CVD) is one of the most common deposition processes employed for depositing layers on a substrate. CVD is a flux-dependent deposition technique that requires precise control of the substrate temperature and the precursors introduced into the processing chamber in order to produce a desired layer of uniform thickness. These requirements become more critical as substrate size increases, creating a need for more complexity in chamber design and gas flow techniques to maintain adequate uniformity.
A variant of CVD that demonstrates excellent step coverage is cyclical deposition or atomic layer deposition (ALD). Cyclical deposition is based upon atomic layer epitaxy (ALE) and employs chemisorption techniques to deliver precursor molecules on a substrate surface in sequential cycles. The cycle exposes the substrate surface to a first precursor, a purge gas, a second precursor and the purge gas. The first and second precursors react to form a product compound as a film on the substrate surface. The cycle is repeated to form the layer to a desired thickness.
Amorphous silicon is widely used in semiconductor devices, flat-panel displays, and solar cells. There remains a key technical challenge for the development of amorphous silicon deposition process with conformality (i.e., good step coverage) or gap-fill performance in high aspect-ratio features. Conventional LPCVD process is limited to high temperature (>550° C.) and low pressure, and, therefore, exhibits poor step coverage and/or gap-fill performance; PECVD process also does not give good step coverage and/or gap-full performance.
Due to the increasing integration of semiconductor circuitry, tungsten has been used based upon superior step coverage. As a result, deposition of tungsten employing CVD techniques enjoys wide application in semiconductor processing due to the high throughput of the process. Depositing tungsten by conventional CVD methods, however, is attendant with several disadvantages.
For example, ALD processes deposit tungsten films into vias containing high aspect ratios (e.g., 20), whereas conventional CVD processes will usually cause similar vias to “pinch-off” and not completely fill. Additionally, tungsten does not readily adhere to some surfaces (e.g., dielectric spacers or oxides). To increase the adhesion of tungsten to dielectric spacers, conventional processes include a TiN layer. The deposition of the TiN film as a seed layer can be time consuming and adds additional complexity to the overall process.
The atomic layer deposition (ALD) of tungsten thin films exhibits very long incubation delay's on silicon, silicon dioxide and titanium nitride services due to poor nucleation performance. A nucleation layer is usually used to mitigate this issue. Conventionally, ALD WSix or WBx is deposited by WF6/Si2H6 and WF6/B2H6, respectively. However, WF6 is directly exposed to the substrate surface (e.g., Si, SiO2) and damages the substrate.
Additionally, ALD tungsten films do not stick well directly on silicon or silicon oxide substrate surfaces. A titanium nitride glue layer is used to improve the adhesion. However, both the titanium nitride glue layer and WSix/WBx nucleation layer do not conduct well, resulting in a very high resistivity for the stack (W/WSix/TiN).
Therefore, there is a need in the art for improved techniques to deposit tungsten layers with decreased resistivity and no barrier/glue layer.